The present invention generally relates to semiconductor devices and more particularly to a compound semiconductor device having a heterostructure and a fabrication process thereof.
Compound semiconductor devices are semiconductor devices constructed on a compound semiconductor material that has a characteristically small effective mass for the electrons, and are used extensively for microwave applications where a high-speed operation of the device is essential. In such compound semiconductor devices, it is possible to design the band structure as desired by using ternary or quarternary compound semiconductor materials.
Compound semiconductor devices include field effect transistors (FETs) and bipolar transistors similarly to Si devices, wherein the compound FETs include HEMTs (High Electron Mobility Transistor) and MESFETs (Metal-Semiconductor FET) as typical examples, while the typical example of a compound bipolar transistor is an HBT (Hetero Bipolar Transistor). In a HEMT, a two-dimensional electron gas associated with a heterojunction interface is used for the carriers and realizes a very high speed operation due to the substantially scatter-free transport of the carriers in the two-dimensional electron gas. In an HBT, on the other hand, a high speed operation and simultaneously a large current gain are realized by using a widegap compound semiconductor material for the emitter in combination with a very thin base layer formed of a compound semiconductor material of a narrow bandgap.
In such conventional compound semiconductor devices, various efforts are being made for increasing the operational speed thereof further. For example, efforts are being made for reducing the gate length as much as possible in FETs such as a HEMT or MESFET. In the case of an HBT, the emitter area is reduced as much as possible.
FIGS. 1A and 1B show a conventional process of fabricating a HEMT.
Referring to FIG. 1A, the HEMT is constructed on a substrate 1 of a semi-insulating GaAs on which a semi-insulating buffer layer 2 of GaAs is formed. On the buffer layer 2, a channel layer 3 of undoped GaAs is formed, and an electron supplying layer 4 of an n-type AlGaAs is formed on the channel layer 3. Further, the electron supplying layer 4 is covered by etching stoppers 5A and 5B both formed of a thin layer of n-type AlGaAs respectively in correspondence to source and drain regions of the HEMT, and cap layers 6A and 6B both of n+-type GaAs are provided on the etching stoppers 5A and 5B respectively.
It should be noted that the HEMT of FIG. 1A further includes a gate electrode 7 of a mushroom type on the electron supplying layer 4 between the source region and the drain region, wherein the gate electrode 7 has a reduced lateral size at a bottom part and an increased lateral size at a top part, and a contact layer 8 of a Ti/Au structure is provided on the gate electrode 7 in conformity with the gate electrode 7.
In the HEMT of such a construction, a deep potential well is formed in the channel layer 3 along an interface between the channel layer 3 and the electron supplying layer 4 as a result of the heterojunction between GaAs forming the channel layer 3 and AlGaAs forming the electron supplying layer 4 and a two-dimensional electron gas is formed in such a deep potential well as is well known in the art.
It should be noted that the gate electrode 7 is formed of WSi of low resistance and establishes a Schottky contact with the electron supplying layer 4. Thereby, the gate electrode 7 controls the transport of the carriers from the source region to the drain region along the two-dimensional gas. By forming the gate electrode 7 in such a mushroom shape, it is possible to reduce the gate length substantially at the bottom part of the gate electrode 7. Further, such a mushroom gate is advantageous for reducing the gate resistance by increasing the gate cross sectional area at the top part thereof, and the operational speed of the HEMT is increased further.
In the construction of the HEMT of FIG. 1A, it should be noted that the mushroom gate 7 is formed first by depositing an insulation film 9 such that the insulation film 9 covers the layered semiconductor body including the foregoing semiconductor layers 1-4, 5A, 5B, 6A and 6B, followed by a formation of a deep contact hole exposing the electron supplying layer 4 in the insulation film 9. After the formation of the deep contact hole, a WSi layer forming the gate electrode 7 and a Ti/Au structure forming the contact layer 8 are deposited consecutively so as to fill the contact hole.
In the HEMT formed as such, it should be noted that the insulation film 9 remains even after the gate electrode 7 and the contact layer 8 thereon are patterned properly. Thereby, there occurs a problem that the insulation film 9 forms a capacitance coupling between the gate electrode 7 and the cap layer 6A or 6B across the insulation film 9 as indicated schematically in FIG. 1A.
As the existence of the cap layer causes a decrease in the operational speed of the HEMT, it has been practiced to remove the insulation film 9 by a wet etching process as indicated in FIG. 1A by arrows. Generally, the insulation film 9 is formed of SiO2 and the wet etching process is conducted by HF.
However, the compound forming the gate electrode 7 is not exactly WSi but a non-stoichiometric compound represented as WSix, and the wet etching process of the insulation film 9 tends to cause the problem that the gate electrode 7 itself is etched during the etching process as indicated in FIG. 1B. When such an etching occurs in the gate electrode 7, there is a substantial risk that the contact between the gate electrode 7 and the electron supplying layer 4 may be impaired.
Further, the wet etching process of the insulation film 9 acts also upon the exposed electron supplying layer 4, wherein such an etching of the electron supplying layer 4 causes an unwanted decrease in the thickness of the electron supplying layer 4 at both sides of the gate electrode 7. When the thickness of the electron supplying layer 4 is reduced as such, there is a substantial risk that the surface depletion region associated with the free surface of the electron supplying layer 4, comes closer to the channel layer 3 or penetrates thereinto. The surface depletion region thus formed tends to expel the two-dimensional electron gas at the both sides of the gate electrode and causes an undesired increase in the parasitic resistance of the HEMT. It should be noted that the foregoing increase of the parasitic resistance appears particularly conspicuously due to the decrease of the gate length of the gate electrode 7 as a result of the erosion. It should be noted that a similar problem occurs not only in a HEMT but also in other FETs such as a MESFET.
Accordingly, it is a general object of the present invention to provide a novel and useful compound semiconductor device wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a fabrication process of a compound semiconductor device including a step of removing an insulation film underneath a gate electrode by a wet etching process, wherein the wet etching process is conducted without etching the gate electrode or a semiconductor layer provided underneath the insulation film in contact with the gate electrode.
Another object of the present invention is to provide a fabrication process of a compound semiconductor device including an etching process, wherein the problem of unwanted etching of a semiconductor layer that is exposed as a result of the etching process, is successfully eliminated.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming an insulation film on a compound semiconductor layer;
forming an opening in said insulation film so as to expose a part of said compound semiconductor layer;
forming a gate electrode of a refractory metal compound on said insulation film such that said gate electrode contacts with said compound semiconductor layer at said contact hole; and
removing said insulation film by a wet etching process;
said wet etching process being conducted by an etchant to which both of said gate electrode and said compound semiconductor layer show a resistance.
Another object of the present invention is to provide a fabrication process of an HBT including a collector layer of a compound semiconductor material, a base layer of a compound semiconductor material and formed on said collector layer, an emitter pattern formed on said base layer, said emitter pattern being formed of a compound semiconductor material having a larger bandgap as compared with said compound semiconductor material forming said base layer, and an emitter electrode of a refractory metal compound formed on said emitter pattern, said method comprising the step of:
reducing an area of said emitter pattern by a wet etching process while using said emitter electrode as a mask;
said wet etching process being conducted by an etchant to which both of said compound semiconductor material forming said base layer and said refractory metal compound forming said emitter electrode show a resistance.
Another object of the present invention is to provide a HEMT, comprising:
a channel layer;
an electron supplying layer provided on said channel layer;
a pair of cap layers provided on said electron supplying layer respectively in correspondence to a source region and a drain region, said pair of cap layers exposing a part of said electron supplying layer between said source region and said drain region; and
a gate electrode of a refractory metal compound provided on said exposed part of said electron supplying layer, said gate electrode having a reduced lateral size in a gate length direction at a bottom part thereof and an increased lateral size in said gate length direction at a top part thereof;
said refractory metal compound being selected from a group consisting of WN, TiW, TiWN;
said electron supplying layer including, at least in a top part thereof, a layer of InGaP with a thickness of about 5 nm.
Another object of the present invention is to provide a MESFET, comprising:
a channel layer;
a pair of cap layers provided on said channel layer respectively in correspondence to a source region and a drain region, said pair of cap layers exposing a part of said channel layer between said source region and said drain region; and
a gate electrode of a refractory metal compound provided on said exposed part of said channel layer, said gate electrode having a reduced lateral size in a gate length direction at a bottom part thereof and an increased lateral size in said gate length direction at a top part thereof;
said refractory metal compound being selected from a group consisting of WN, TiW, TiWN;
said channel layer including, at least in a top part thereof, a layer of InGaP with a thickness of about 5 nm.
Another object of the present invention is to provide a HBT, comprising:
a collector layer of a compound semiconductor material;
a base layer of a compound semiconductor material, provided on said collector layer;
an emitter pattern provided on said base layer, said emitter pattern comprising a compound semiconductor material having a larger bandgap as compared with said compound semiconductor material forming said base; and
an emitter electrode provided on said emitter pattern;
said base layer including a layer of InGaP having a thickness of about 5 nm in a top part thereof.
According to the present invention, the problem of erosion of the gate electrode as well as the semiconductor layer contacting the gate electrode at the time of the wet etching is successfully eliminated, and a high-speed semiconductor device having a reduced gate length is obtained. Further, the present invention is not only effective for FETs such as HEMT or MESFET but also to bipolar transistors such as HBT.